The invention relates to ESD protection devices. More particularly, it relates to ESD protection devices that are implemented using BiCMOS technology.
Analog circuits typically display sensitivity to excessive voltage levels. Transients, such as electrostatic discharges (ESD) can cause the voltage handling capabilities of the analog circuit to be exceeded, resulting in damage to the analog circuit. ESD protection devices have, therefore, been devised to shunt current to ground during excessive voltage peaks.
In the case of BiCMOS technology, it is clearly preferable that the protection device be implemented using standard BiCMOS process techniques. Furthermore, one of the difficulties encountered in designing such protection circuitry is that the specifications for these clamps have to fit within a relatively small design window that, on the one hand, must take into account the breakdown voltage of the circuit being protected, and, on the other hand, avoid latch-up under normal operation. Thus, the clamp must be designed so as to be activated below the breakdown voltage of the circuit that is to be protected. At the same time, the latch-up or holding voltage must exceed the normal operating voltage of the protected circuit.
One possible ESD protection device involves the use a silicon-controlled rectifier (SCR). This is a device that provides an open circuit between a first node and a second node when the voltage across the first and second nodes is positive and less than a trigger voltage. When the voltage across the first and second nodes rises to be equal to or greater than the trigger voltage, the SCR provides a low-resistance current path between the first and second nodes. Further, once the low-resistance current path has been provided, the SCR maintains the current path as long as the voltage across the first and second nodes is equal to or greater than a holding voltage that is lower than the trigger voltage. As a result of these characteristics, SCRs have been used to provide ESD protection, in which the first node corresponds to a to-be-protected node, and the second node is typically connected to ground. The SCR operates within an ESD protection window that has a maximum voltage defined by the destructive breakdown level of the to-be-protected node, and a minimum voltage (also known as a latch-up voltage) defined by any dc bias on the to-be-protected node.
Thus, when the voltage across the to-be-protected node and the second node is less than the trigger voltage, the SCR provides an open circuit between the to-be-protected node and the second node. However, when the to-be-protected node receives a voltage spike that equals or exceeds the trigger voltage, such as when an ungrounded human-body discharge occurs, the SCR provides a low-resistance current path from the to-be-protected node to the second node. In addition, once the ESD event has passed and the voltage on the to-be-protected node falls below the holding voltage, the SCR again provides an open circuit between the to-be-protected node and the second node.
However, a disadvantage of a SCR is that it typically displays a very low holding voltage, thus exposing the device to latch-up. Therefore, the SCR may remain in conduction after an ESD pulse if the voltage does not drop back down to below the holding voltage. For example, the bias voltage may keep the voltage above the holding voltage. Since the SCR is designed for short, high current pulses, extended conduction during normal operation can cause hot carrier degradation and ultimately failure of the device.
It is therefore desirable to have a protection structure that has a high holding voltage.
Another issue is providing protection for dual output circuits. In the case of BiCMOS output interface circuits that allow dual polarity of the output voltage amplitude (so-called xe2x80x9cswingxe2x80x9d), conventional triggering ESD structures such as SCRS, LVTSCRs, GGNMOS, TFO devices and even diode pairs are unsuitable. When these devices are reverse biased or a reverse power supply is applied, a substantial amount of power is consumed by the internal diode structure, as is discussed in greater detail below.
The ESD protection device or triggering structure for dual polarity applications should therefore display an S-shaped I-V characteristic for voltage swings in both directions. Bi-directional thyristor devices such as TRIACs (triode AC switches) and DIACS (diode AC switches) (for example AC trigger diodes and bi-directional p-n-p-n diode switches) exist that provide for bi-direcdonal voltage swings. However, as mentioned above, ESD protection devices require specific functional specifications in order to operate within a specific window. The triggering voltage may not be too high, to avoid damage to the circuit being protected. Also, the triggering structure must not remain in conduction once the ESD pulse has passed and normal voltages resume. Thus, the holding voltage of the device must, again, be sufficiently high to avoid latch-up during normal operation.
The present invention provides a method and triggering ESD SCR structure that can readily be implemented in BiCMOS technology and which provides an increased holding voltage or bi directional voltage swings. The present invention also provides a method and triggering structure that displays a high holding voltage and is suitable of protecting circuits that experience dual voltage swings.
The present invention provides both a SCR structure and a Bi-CMOS ESD protection structure with dual voltage capabilities, wherein the structures provide increased holding voltages over conventional SCR devices. This is achieved by providing a n-buried layer (NBL) of suitable length in the structure.
The dual voltage device is created by forming two laterally spaced p-regions in a n-material and defining a n+ region and a p+ region connected by a common contact, in each of the p-regions. In this way a device is defined that has I-V characteristics that are similar to those defined by a SCR device in a positive direction, but, in this case, having those characteristics in both directions. The device may be asymmetrical to accommodate different voltage amplitudes in the positive and negative directions.
According to the invention, there is provided a SCR with a high holding voltage comprising a SCR structure in which a n-buried layer (NBL) has been formed, wherein the length of the NBL is chosen to provide a desired holding voltage.
Further, according to the invention, there is provided a SCR structure, comprising a p-region formed in a n-epitaxial layer, a n-region formed in the n-epitxial layer, a first n+ region and a first p+ region formed in the p-region, and connected by a first common contact, a second n+ region and a second p+ region formed in the n-region, and connected by a second common contact, and a n-buried layer (NBL) formed in the n-material. The NBL may be symmetrically or asymmetrically located relative to the n-region and the p-region.
Further, according to the invention, there is provided a bi-directional ESD protection structure having a first p-region formed in a n-material; a second p-region formed in the n-material and laterally spaced from the first p-region; a first n+ region and a first p+ region formed in the first p-region, and connected by a first common contact, a second n+ region and a second p+ region formed in the second p-region, and connected by a second common contact, and a n-buried layer formed in the n-material. One or both of the p-regions may comprises a p-deep region, a p-well, or a p-body. A shallow trench isolation region or thick field oxide may be formed between the first p-region and the second p-region. Furthermore, a sinker region may be formed between the first p-region and the second p-region.
Further, according to the invention, there is provided a method of forming a bi-directional ESD protection device, comprising providing a semiconductor substrate, n-doping at least part of the semiconductor substrate to form n-material, masking and doping the n-material to define a first and a second p-region in the n-material that are laterally spaced from each other, forming a n+ region and a p+ region laterally spaced from each other, in each of the two p-regions, providing a common contact for both of the n+ region and p+ region of the two p-regions, and providing a n-buried layer (NBL) in the n-material. The size of the NBL may be chosen to provide the desired holding voltage, and the location of the NBL may be chosen to provide different I-V characteristics in the positive and the negative directions. Ideally BiCMOS technology is used in the process steps. Typically the n+ region and p+ region in each of the p-regions are formed by masking and doping the p-regions. The p-regions may be defined by one or more of a p-well, p-body, collector, or p-deep type implant. The method may include n-doping the region between the p-regions to define a higher doped region between the p-regions, for example, forming a sinker region between the p-regions. The size and location of the higher doped region between the p-regions may be chosen to achieve desired triggering and holding voltage characteristics for the device. The method may further include forming one or more ISO or lightly doped regions in the n-material. Also, the first p-region may be different from the second p-region to define an asymmetrical structure. This difference in the p-regions may be in one or more of the doping level, thickness, and width of the p-regions.